Manufacture of a semiconductor device is normally divided into two major phases. The “front end of the line” (FEOL) is dedicated to the creation of all the transistors in the body of the semiconductor device, and the “back end of the line” (BEOL) creates the metal interconnect structures, which connect all the transistors with each other as well as with the external world. The FEOL consists of a repeated sequence of steps that modifies the electrical properties of part of a wafer surface and grows new material above selected regions. Once all active components are created, the second phase of manufacturing (BEOL) begins. During the BEOL, metal interconnects are created to establish the connection pattern of the semiconductor device.
Semiconductor devices generally include a plurality of circuits which form an integrated circuit fabricated on a semiconductor substrate. To improve the performance of the circuits, low k dielectric materials having a dielectric constant of less than silicon dioxide, such as porous dielectric materials, have been used as inter-layer dielectric (ILD) to further reduce capacitance. Interconnect structures made of metal lines or vias are usually formed in and around the porous dielectric material ILD to connect elements of the circuits. An interconnect structure may consist of multilevel or multilayered schemes, such as, for example, single or dual damascene wiring structures. Within a typical interconnect structure, metal lines run parallel to the semiconductor substrate, while metal vias run perpendicular to the semiconductor substrate.
The quality of the metal lines and metal vias is extremely important to ensure yield and reliability. The major problem encountered in this area today is poor mechanical strength of deep submicron metal contacts (lines and vias) embedded in low k dielectric materials, which can cause unsatisfied thermal cycling and stress migration resistance in the interconnect structures. This problem becomes more severe when new metallization approaches or porous low k dielectric materials are used.
To solve the weak mechanical strength issue while employing copper damascene and low k dielectric materials in an interconnect structure, a so called “via punch-through” technique has been adopted by the semiconductor industry. The “via punch-through” technique provides a via gouging feature as anchoring area within the lower part of the interconnect structure. The via gouging feature helps to achieve an improved electrical contact resistance as well as a reasonable reliability requirement through increasing mechanical strength of the metal contacts.
FIGS. 1A-1E illustrate processing steps of a conventional process for forming an interconnect structure with a via gouging feature. FIG. 1A illustrates a prior art interconnect structure that is formed after a dual damascene patterning process. The interconnect structure has an upper interconnect level 108 which is located atop a lower interconnect level 100. The lower interconnect level 100 includes a first dielectric material 102 and a copper interconnect 104. The lower interconnect level 100 is separated in part from the upper interconnect level 108 by a dielectric capping layer 106. The upper interconnect level 108 includes a second dielectric material 110 that includes both line openings 112 and a via opening 114 located therein. A top surface of the copper interconnect 104 of the lower interconnect level 100 that is beneath the via opening 114 is exposed.
In FIG. 1B, a diffusion barrier 116, such as TaN, is formed over all of the exposed surfaces, including the sidewalls and bottom horizontal surfaces of the line openings 112 and the via opening 114. In FIG. 1C, argon sputtering is used to clean the bottom horizontal surface of the via opening 114 and to form a gouging feature 118 into the copper interconnect 104 of the lower interconnect level 100. The gouging feature 118 enhances the interconnect strength between the various interconnect levels shown. As shown in FIG. 1C, during the argon sputtering process, the diffusion barrier located at the bottom horizontal surface of each of the line openings 112 is also removed. Due to the inherent aggressive nature of the argon sputtering process, dielectric damages 120 are also formed in the second dielectric material 110 near the bottom of each of the line openings 112.
FIG. 1D shows the prior art interconnect structure of FIG. 1C after forming a metal liner layer 122 on all of the exposed surfaces. In FIG. 1E, the line openings 112 and the via opening 114 are filled with a conductive metal 124, such as copper. As shown in FIG. 1E, the prior art interconnect structure has poor diffusion barrier coverage and a bottom roughness at the bottom of the metal filled lines 112 (designated by reference numeral 126), as a result of the dielectric damages 120 formed into the second low k dielectric material 110. Both of these characteristics reduce the quality of the diffusion barrier 116 and degrade the overall wiring reliability.